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<title>Qucs - Getting Started Digital</title>
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<center><h3>
- Qucs -<br>
Quite Universal Circuit Simulator<br>
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<h1>
Getting Started with<br>
Digital Simulations<br><br>
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Qucs is also a graphical user interface for performing digital simulations.
This document should give you a short description on how to use it.
<br><br>
For digital simulations Qucs uses the FreeHDL program
(<a href="http://www.freehdl.seul.org">http://www.freehdl.seul.org</a>).
So the FreeHDL package as well as the GNU C++ compiler must be installed
on the computer.<br><br>
There is no big difference in running an analog or a digital
simulation. So having read the <a href="start.html">Getting Started for
analog simulations</a>, it is now easy to get a digital simulation work.
Let us compute the truth table of a simple logical AND cell.
Select the digital components in the combobox of the components tab on
the left-hand side and build the circuit shown in figure 1. The digital
simulation block can be found among the other simulation blocks.<br>
The digital sources <i>S1</i> and <i>S2</i> are the inputs, the node labeled
as <i>Output</i> is the output. After performing the simulation, the
data display page opens. Place the diagram <i>truth table</i> on it
and insert the variable <i>Output</i>. Now the truth table of a
two-port AND cell is shown. Congratulation, the first digital simulation
is done!
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<img src="qucsdigi.png"><br>Figure 1 - Qucs main window<br><br>
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A truth table is not the only digital simulation that Qucs can perform.
It is also possible to apply an arbitrary signal to a circuit and see
the output signal in a timing diagram. To do so, the parameter <i>Type</i>
of the simulation block must be changed to <i>TimeList</i> and the
duration of the simulation must be entered in the next parameter.
The digital sources have now a different meaning: They can output an
arbitrary bit sequence by defining the first bit (low or high) and
a list that sets the times until the next change of state. Note that
this list repeats itself after its end. So, to create a 1GHz clock
with pulse ratio 1:1, the list writes: 0.5ns; 0.5ns<br>
To display the result of this simulation type, there is the diagram
<i>timing diagram</i>. Here, the result of all output nodes can be shown
row by row in one diagram. So, let's have fun...
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<br>
<h3>VHDL File Component</h3>
More complex and more universal simulations can be performed using the
component "VHDL file". This component can be picked up from the component
list view (section "digital components"). Nevertheless the recommended
usage is the following: The VHDL file should be a member of the project.
Then go to the content list view and click on the file name. After entering
the schematic area, the VHDL component can be placed.<br>
The last entity block in the VHDL file defines the interface, that is, all
input and output ports must be declared here. These ports are also shown by the
schematic symbol and can be connected to the rest of the circuit. During
simulation the source code of the VHDL file is placed into the top-level
VHDL file. This must be considered as it causes some limitations. For
example, the entity names within the VHDL file must differ from names
already given to subcircuits. (After a simulation, the complete source
code can be seen by pressing F6. Use it to get a feeling for this procedure.)

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